As semiconductor devices continue to become smaller in size, the devices must be what is known in the industry as “scalable”. That is, the devices must continue to be able to be made with reduced dimensions and still function at the required specifications. Traditionally, MOSFETs have been implemented with a single control electrode or gate on a planar substrate. The gate is placed between a source and drain electrode and functioned to create a channel for controlling the amount of current conducted by the MOSFET. Because there is a gate electrode to control the channel only on one side of the channel, there is only a single source of control of the channel. Single control of the channel leads to undesired leakage current (i.e. electron or hole flow) between the source and drain when the transistor is intended to be non-conductive.
An improved structure that was proposed was the use of a two-gate transistor with the gates on both sides of a thin silicon channel. This arrangement increases the electrostatic coupling between the gates and the channel relative to the single gate device. As a result, the drive current of the transistor is increased and the leakage current is decreased. One type of transistor having two gates is known in the art as double gate or dual gate FinFETs, in which the channel consists of a single pillar or slab (a fin) that is oriented perpendicular to the plane of a substrate for a given area overlying the substrate. Additional channel width for a transistor requires additional circuit area to provide the additional channel width. For example, known planar MOSFETs and FINFETs having multiple channels are formed laterally and thus require significant additional area.
The effective channel width of a FinFET transistor is only on the surface of a single silicon fin. The dimensions of the fin determine the characteristics of the device. It is desirable that the fin be thinner than the gate length in order to get good short channel control. However, lithographically or spacer defined dimensions do not offer as much manufacturing control as grown layers to form a transistor channel.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.